View 9LPRS365BKLF_6989542.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ics9lprs365 datasheet 1218?09/01/10 recommended application: ck505 compliant clock with fully integrated voltage regulator and internal series resistor on differential outputs output features: ? 2 - cpu differential low power push-pull pairs ? 9 - src differential low power push-pull pairs ? 1 - cpu/src selectable differential low power push-pull pair ? 1 - src/dot selectable differential low power push-pull pair ? 5 - pci, 33mhz ? 1 - pci_f, 33mhz free running ? 1 - usb, 48mhz ? 1 - ref, 14.318mhz key specifications: ? cpu outputs cycle-cycle jitter < 85ps ? src output cycle-cycle jitter < 125ps ? pci outputs cycle-cycle jitter < 250ps ? +/- 100ppm frequency accuracy on cpu & src clocks features/benefits: ? does not require external pass transistor for voltage regulator ? integrated 33ohm series resistors on differential outputs, z o =50 ? supports spread spectrum modulation, default is 0.5% down spread ? uses external 14.318mhz crystal, external crystal load caps are required for frequency tuning ? selectable between one src differential push-pull pair and two single-ended outputs 64-pin ck505 w/fully integrated voltage regulator + integrated series resistor fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 0 0 0 266.66 0 0 1 133.33 0 1 0 200.00 0 1 1 166.66 1 0 0 333.33 1 0 1 100.00 1 1 0 400.00 11 1 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. 96.00 reserved 100.00 33.33 14.318 48.00 table 1: cpu fre q uenc y select table 64-tssop 27_select (power on latch) 0 1 dot96, lcd_ss src0, 27mhz non ss & ss byte1 bit7 = 1. byte1 bit7 = 0. pin13/14 & pin17/18 pin configuration pci0/cr#_a 1 64 sclk vddpci 2 63 sdata pci1/cr#_b 3 62 ref0/fslc/test_sel pci2/tme 4 61 vddref pci3 5 60 x1 pci4 /27_select 659x2 pci_f5/itp_en 7 58 gndref gndpci 8 57 fslb/test_mode vdd48 9 56 ck_pwrgd/pd# usb_48mhz/fsla 10 55 vddcpu gnd4811 54cput0 vdd96_io 12 53 cpuc0 srct0/dott_96 13 52 gndcpu srcc0/dotc_96 14 51 cput1_f gnd 15 50 cpuc1_f vddpll3 16 49 vddcpu_io 27mhz_nonss/srct1/se1 17 48 nc 27mhz_ss/srcc1/se2 18 47 cput2_itp/srct8 gnd 19 46 cpuc2_itp/srcc8 vddpll3_io 20 45 vddsrc_io srct2/s atat 21 44 srct7/ cr#_f srcc2/satac 22 43 srcc7/cr#_e gndsrc 23 42 gndsrc srct3/cr#_c 24 41 srct6 srcc3/cr#_d 25 40 srcc6 vddsrc_io 26 39 vddsrc srct427 38pci_stop# srcc4 28 37 cpu_stop# gndsrc 29 36 vddsrc_io srct930 35srcc10 srcc9 31 34 srct10 srcc11/cr#_g 32 33 srct11/cr#_h 64-tssop * internal pull-up resistor ** internal pull-down resistor 9lprs365
2 ics9lprs365 datasheet 1218?09/01/10 tssop pin description pin # pin name type description 1 pci0/cr#_a i/o 3.3v pci clock output or clock request control a for either src0 or src2 pair the power-up default is pci0 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 0 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_a_en bit located in byte 5 of smbus address space. byte 5, bit 7 0 = pci0 enabled (default) 1= cr#_a enabled. byte 5, bit 6 controls whether cr#_a controls src0 or src2 pair byte 5, bit 6 0 = cr#_a controls src0 pair (default), 1= cr#_a controls src2 pair 2 vddpci pwr power supply pin for the pci outputs, 3.3v nominal 3 pci1/cr#_b i/o 3.3v pci clock output/clock request control b for either src1 or src4 pair the power-up default is pci1 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 1 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_b_en bit located in byte 5 of smbus address space. byte 5, bit 5 0 = pci1 enabled (default) 1= cr#_b enabled. byte 5, bit 6 controls whether cr#_b controls src1 or src4 pair byte 5, bit 4 0 = cr#_b controls src1 pair (default) 1= cr#_b controls src4 pair 4 pci2/tme i/o 3.3v pci clock output / trusted mode enable (tme) latched input. this pin is sampled on power-up as follows 0 = overclocking of cpu and src allowed 1 = overclocking of cpu and src not allowed after being sampled on power-up, this pin becomes a 3.3v pci output 5 pci3 out 3.3v pci clock output. 6 pci4/27_select i/o 3.3v pci clock output / 27mh mode select for pin17, 18 strap. on powerup, the logic value on this pin determines the power-up default of dot_96/src0 and 27mhz/src1 output and the function table for the pin17 and pin18. 7 pci_f5/itp_en i/o free running pci clock output and itp/src8 enable strap. this output is not affected by the state of the pci_stop# pin. on powerup, the state of this pin determines whether pins 46 and 47 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 8 gndpci pwr ground for pci clo cks. 9 vdd48 pwr power supply for usb clock, nominal 3.3v. 10 usb_48mhz/fsla i/o fixed 48mhz usb clock output. 3.3v./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 11 gnd48 pwr ground pin for the 48mhz outputs. 12 vdd96_io pwr 1.05v to 3.3v from external power supply 13 dott_96/srct0 out true clock of src or dot96. the power-up default function depends on 27_select, 1= src0, 0=dot96 14 dotc_96/srcc0 out complement clock of src or dot96. the power-up default function depends on 27_select, 1= src0, 0=dot96 15 gnd pwr ground pin for the dot96 clocks. 16 vdd pwr power supply for src / se1 and se2 clocks, 3.3v nominal.
3 ics9lprs365 datasheet 1218?09/01/10 tssop pin description (continued) pin # pin name type description 17 27mhz_nonss/srct1/se1 out true clock of differential src1 clock pair / 3.3v single-ended output. 27_select determines the power-up default, 1=27mhz non-spread se clock, 0 = lcd_sst 100mhz differential clock. see table 2 for more information. 18 27mhz_ss/srcc1/se2 out complement clock of differential src1 clock pair / 3.3v single-ended output. 27_select determines the power-up default, 1=27mhz spread se clock, 0 = lcd_ssc 100mhz differential clock. see table 2 for more information. 19 gnd pwr ground pin for src / se1 and se2 clocks, pll3. 20 vddpll3_io pwr 1.05v to 3.3v from external power supply 21 srct2/satat out true clock of differential src/sata clock pair. 22 srcc2/satac out complement clock of differential src/sata clock pair. 23 gndsrc pwr ground pin for src clocks. 24 srct3/cr#_c i/o true clock of differential src clock pair/ clock request control c for either src0 or src2 pair the power-up default is srcclk3 output, but this pin may also be used as a clock r equest control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_c_en bit located in byte 5 of smbus address space. byte 5, bit 3 0 = src3 enabled (default) 1= cr#_c enabled. byte 5, bit 2 controls whether cr#_c controls src0 or src2 pair byte 5, bit 2 0 = cr#_c controls src0 pair (default), 1= cr#_c controls src2 pair 25 srcc3/cr#_d i/o complementary clock of differential src clock pair/ clock request control d for either src1 or src4 pair the power-up default is srcclk3 output, but this pin may also be used as a clock r equest control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_d_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= cr#_d enabled. byte 5, bit 0 controls whether cr#_d controls src1 or src4 pair byte 5, bit 0 0 = cr#_d controls src1 pair (default), 1= cr#_d controls src4 pair 26 vddsrc_io pwr 1.05v to 3.3v from external power supply 27 srct4 i/o true clock of differential src clock pair 4 28 srcc4 i/o complement clock of differential src clock pair 4 29 gndsrc pwr ground pin for src clocks. 30 srct9 out true clock of differential src clock pair. 31 srcc9 out complement clock of differential src clock pair. 32 srcc11/cr#_g i/o src11 complement /clock request control for src9 pair the power-up default is src11#, but this pin may also be used as a clock request control of src9 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src9 pair using byte 6, bit 5 of smbus configuration space byte 6, bit 5 0 = src11# enabled (default) 1= cr#_g controls src9
4 ics9lprs365 datasheet 1218?09/01/10 tssop pin description (continued) pin # pin name type description 33 srct11/cr#_h i/o src11 true or clock request control h for src10 pair the power-up default is src11, but this pin may also be used as a clock request control of src10 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src10 pair using byte 6, bit 4 of smbus configuration space byte 6, bit 4 0 = src11 enabled (default) 1= cr#_h controls src10. 34 srct10 out true clock of differential src clock pair. 35 srcc10 out complement clock of differential src clock pair. 36 vddsrc_io pwr 1.05v to 3.3v from external power supply 37 cpu_stop# in stops all cpu clocks, except those set to be free r unning clo cks. in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fsa values 38 pci_stop# in stops all pci clocks, except those set to be free running clocks. in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fsa values 39 vddsrc pwr vdd pin for src pre-drivers, 3.3v nominal 40 srcc6 out complement clock of low power differential src clock pair. 41 srct6 out true clock of low power differential src clock pair. 42 gndsrc pwr ground for src clocks 43 srcc7/cr#_e i/o src7 complement or clock request control e for src6 pair the power-up default is src7#, but this pin may also be used as a clock request control of src6 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cr#_e controls src6. 44 srct7/cr#_f i/o src7 true or clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src8 pair usin g byte 6, bit 6 of smbus confi g uration space byte 6, bit 6 0 = src7# enabled (default) 1 = cr#_f controls src8. 45 vddsrc_io pwr 1.05v to 3.3v from external power supply 46 cpuc2_itp/srcc8 out complement clock of low power differential cpu2/complement clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8# 1 = itp# 47 cput2_itp/srct8 out true clock of low power differential cpu2/true clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8 1 = itp 48 nc n/a no connect
5 ics9lprs365 datasheet 1218?09/01/10 tssop pin description (continued) pin # pin name type description 49 vddcpu_io pwr 1.05v to 3.3v from external power supply 50 cpuc1_f out complement clock of low power differenatial cpu clock pair. this clock w ill be free-running during iamt. 51 cput1_f out true clock of low power differential cpu c lock pair. this clock will be free-running during iamt. 52 gndcpu pwr ground pin for cpu outputs 53 cpuc0 out complement clock of low power differential cpu clock pair. 54 cput0 out true clock of low power differential cpu clock pair. 55 vddcpu pwr power supply 3.3v nominal. 56 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 57 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table. 58 gndref pwr ground pin for crystal osc illator c ircuit 59 x2 out crystal output, nominally 14.318mhz. 60 x1 in crystal input, nominally 14.318mhz. 61 vddref pwr power pin for the ref outputs, 3.3v nominal. 62 ref0/fslc/test_sel i/o 3.3v 14.318mhz reference clock/3.3v tolerant low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values/ test_sel: 3-level latched input to enable test mode. refer to test clarification table. 63 sdata i/o data pin for smbus circuitry, 5v tolerant. 64 sclk in clock pin of smbus circuitry, 5v tolerant.
6 ics9lprs365 datasheet 1218?09/01/10 pin configuration 64-pin mlf fslb/test_mode ck_pwrgd/pd# vddcpu cput0 cpuc0 gndcpu cput1_f cpuc1_f vddcpu_io nc cput2_itp/srct8 cpuc2_itp/srcc8 vddsrc_io srct7/cr#_f srcc7/cr#_e gndsrc 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 gndref 1 48 srct6 x2 2 47 srcc6 x1 3 46 vddsrc vddref 4 45 pci_stop# ref0/fslc/test_sel 5 44 cpu_stop# sdata 6 43 vddsrc_io sclk 7 42 srcc10 pci0/cr#_a 8 41 srct10 vddpci 9 40 srct11/cr#_h pci1/cr#_b 10 39 srcc11/cr#_g pci2/tme 11 38 srcc9 pci3 12 37 srct9 pci4/27_select 13 36 gndsrc pci_f5/itp_en 14 35 srcc4 gndpci 15 34 srct4 vdd48 16 33 vddsrc_io 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 usb_48mhz/fsla gnd48 vdd96_io srct0/dott_96 srcc0/dotc_96 gnd vddpll3 27mhz_nonss/srct1/se1 27mhz_ss/srcc1/se2 gnd vddpll3_io srct2/satat srcc2/satac gndsrc srct3/cr#_c srcc3/cr#_d 9lprs365 64-mlf 27_select (power on latch) 0 1 dot96, lcd_ss src0, 27mhz non ss & ss byte1 bit7 = 1 byte1 bit7= 0. pin20/21 & pin24/25
7 ics9lprs365 datasheet 1218?09/01/10 mlf pin description pin # pin name type description 1 gndref pwr gr ound pin for crystal osc illator circuit 2 x2 out crystal output, nominally 14.318mhz. 3 x1 in crystal input, nominally 14.318mhz. 4 vddref pwr power pin for the ref outputs, 3.3v nominal. 5 ref0/fslc/test_sel i/o 3.3v 14.318mhz reference clock/3.3v tolerant low threshold input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values/ test_sel: 3-level latched input to enable test mode. refer to test clarification table. 6 sdata i/o data pin for smbus circuitry, 5v tolerant. 7 sclk in clock pin of smbus circuitry, 5v tolerant. 8 pci0/cr#_a i/o 3.3v pci clock output or clock request control a for either src0 or src2 pair the power-up default is pci0 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 0 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_a_en bit located in byte 5 of smbus address space. byte 5, bit 7 0 = pci0 enabled (default) 1= cr#_a enabled. byte 5, bit 6 controls whether cr#_a controls src0 or src2 pair byte 5, bit 6 0 = cr#_a controls src0 pair (default), 1= cr#_a controls src2 pair 9 vddpci pwr power supply pin for the pci outputs, 3.3v nominal 10 pci1/cr#_b i/o 3.3v pci clock output/clock request control b for either src1 or src4 pair the power-up default is pci1 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the pci output must first be disabled in byte 2, bit 1 of smbus address space . after the pci output is disabled (high-z), the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_b_en bit located in byte 5 of smbus address space. byte 5, bit 5 0 = pci1 enabled (default) 1= cr#_b enabled. byte 5, bit 6 controls whether cr#_b controls src1 or src4 pair byte 5, bit 4 0 = cr#_b controls src1 pair (default) 1= cr#_b controls src4 pair 11 pci2/tme i/o 3.3v pci clock output / trusted mode enable (tme) latched input. this pin is sampled on power-up as follows 0 = overclocking of cpu and src allowed 1 = overclocking of cpu and src not allowed after being sampled on power-up, this pin becomes a 3.3v pci output 12 pci3 out 3.3v pci clock output. 13 pci4/27_select i/o 3.3v pci clock output / 27mh mode select for pin24, 25 strap. on powerup, the logic value on this pin determines the power-up default of dot_96/src0 and 27mhz/src1 output and the function talbe for the pin24 and pin25. 14 pci_f5/itp_en i/o free running pci clock output and itp/src8 enable strap. this output is not affected by the state of the pci_stop# pin. on powerup, the state of this pin determines whether pins 53 and 54 are an itp or src pair. 0 =src8/src8# 1 = itp/itp# 15 gndpci pwr ground for pci clo cks. 16 vdd48 pwr power supply for usb clock, nominal 3.3v.
8 ics9lprs365 datasheet 1218?09/01/10 mlf pin description (continued) pin # pin name type description 17 usb_48mhz/fsla i/o fixed 48mhz usb clock output. 3.3v./ 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. 18 gnd48 pwr ground pin for the 48mhz outputs. 19 vdd96_io pwr 1.05v to 3.3v from external power supply 20 dott_96/srct0 out true clock of src or dot96. the power-up default function depends on 27_select, 1= src0, 0=dot96 21 dotc_96/srcc0 out complement clock of src or dot96. the power-up default function depends on 27_select,1= src0, 0=dot96 22 gnd pwr ground pin for the dot96 clo cks. 23 vdd pwr power supply for src / se1 and se2 clocks, 3.3v nominal. 24 27mhz_nonss/srct1/se1 out true clock of differential src1 clock pair / 3.3v single-ended output. 27_select determines the power-up default, 1=27mhz non-spread se clock, 0 = lcd_sst 100mhz differential clock. see table 2 for more information. 25 27mhz_ss/srcc1/se2 out complement clock of differential src1 clock pair / 3.3v single-ended output. 27_select determines the power-up default, 1=27mhz spread se clock, 0 = lcd_ssc 100mhz differential clock. see table 2 for more information. 26 gnd pwr ground pin for src / se1 and se2 clo cks, p ll3. 27 vddpll3_io pwr 1.05v to 3.3v from external power supply 28 srct2/satat out true clock of differential src/sata clock pair. 29 srcc2/satac out complement clock of differential src/sata clock pair. 30 gndsrc pwr ground pin for src clo cks. 31 srct3/cr#_c i/o true clock of differential src clock pair/ clock request control c for either src0 or src2 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 0 or src pair 2 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 2 or pair 0 using the cr#_c_en bit located in byte 5 of smbus address space. byte 5, bit 3 0 = src3 enabled (default) 1= cr#_c enabled. byte 5, bit 2 controls whether cr#_c controls src0 or src2 pair byte 5, bit 2 0 = cr#_c controls src0 pair (default), 1= cr#_c controls src2 pair 32 srcc3/cr#_d i/o complementary clock of differential src clock pair/ clock request control d for either src1 or src4 pair the power-up default is srcclk3 output, but this pin may also be used as a clock request control of src pair 1 or src pair 4 via smbus. before configuring this pin as a clock request pin, the src3 output must first be disabled in byte 4, bit 7 of smbus address space . after the src3 output is disabled, the pin can then be set to serve as a clock request pin for either src pair 1 or pair 4 using the cr#_d_en bit located in byte 5 of smbus address space. byte 5, bit 1 0 = src3 enabled (default) 1= cr#_d enabled. byte 5, bit 0 controls whether cr#_d controls src1 or src4 pair byte 5, bit 0 0 = cr#_d controls src1 pair (default), 1= cr#_d controls src4 pair
9 ics9lprs365 datasheet 1218?09/01/10 mlf pin description (continued) pin # pin name type description 33 vddsrc_io pwr 1.05v to 3.3v from external power supply 34 srct4 i/o true clock of differential src clock pair 4 35 srcc4 i/o complement clock of differential src clock pair 4 36 gndsrc pwr ground pin for src clo cks. 37 srct9 out true clock of differential src clock pair. 38 srcc9 out complement clock of differential src clock pair. 39 srcc11/cr#_g i/o src11 complement /clock request control for src9 pair the power-up default is src11#, but this pin may also be used as a clock request control of src9 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src9 pair using byte 6, bit 5 of smbus configuration space byte 6, bit 5 0 = src11# enabled (default) 1= cr#_g controls src9 40 srct11/cr#_h i/o src11 true or clock request control h for src10 pair the power-up default is src11, but this pin may also be used as a clock request control of src10 via smbus. before configuring this pin as a clock request pin, the src11 output pair must first be disabled in byte 3, bit 7 of smbus configuration space after the src11 output is disabled (high-z), the pin can then be set to serve as a clock request for src10 pair using byte 6, bit 4 of smbus configuration space byte 6, bit 4 0 = src11 enabled (default) 1= cr#_h controls src10. 41 srct10 out true clock of differential src clock pair. 42 srcc10 out complement clock of differential src clock pair. 43 vddsrc_io pwr 1.05v to 3.3v from external power supply 44 cpu_stop# in stops all cpu clocks, except those set to be free running clocks. in amt m ode 3 bits are shifted in from the ich to set the fsc, fsb, fsa values 45 pci_stop# in stops all pci clocks, except those set to be free running clo cks. in amt mode 3 bits are shifted in from the ich to set the fsc, fsb, fsa values 46 vddsrc pwr vdd pin for src pre-drivers, 3.3v nominal 47 srcc6 out complement clock of low power differential src clock pair. 48 srct6 out true clock of low power differential src clock pair.
10 ics9lprs365 datasheet 1218?09/01/10 mlf pin description (continued) pin # pin name type description 49 gndsrc pwr ground for src clocks 50 srcc7/cr#_e i/o src7 complement or clock request control e for src6 pair the power-up default is src7#, but this pin may also be used as a clock request control of src6 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space . after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src6 pair using byte 6, bit 7 of smbus configuration space byte 6, bit 7 0 = src7# enabled (default) 1= cr#_e controls src6. 51 srct7/cr#_f i/o src7 true or clock request control 8 for src8 pair the power-up default is src7, but this pin may also be used as a clock request control of src8 via smbus. before configuring this pin as a clock request pin, the src7 output pair must first be disabled in byte 3, bit 3 of smbus configuration space after the src output is disabled (high-z), the pin can then be set to serve as a clock request for src8 pair using byte 6, bit 6 of smbus configuration space byte 6, bit 6 0 = src7# enabled (default) 1 = cr#_f controls src8. 52 vddsrc_io pwr 1.05v to 3.3v from external power supply 53 cpuc2_itp/srcc8 out complement clock of low power differential cpu2/complement clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8# 1 = itp# 54 cput2_itp/srct8 out true clock of low power differential cpu2/true clock of differential src pair. the function of this pin is determined by the latched input value on pin 7, pcif5/itp_en on powerup. the function is as follows: pin 7 latched input value 0 = src8 1 = itp 55 nc n/a no connect 56 vddcpu_io pwr 1.05v to 3.3v from external power s upply 57 cpuc1_f out complement clock of low power differenatial cpu clock pair. this clock w ill be free-running during iamt. 58 cput1_f out true clock of low power differential cpu clock pair. this clock will be free-running during iamt. 59 gndcpu pwr gr ound pin for cpu outputs 60 cpuc0 out complement clock of low power differential cpu clock pair. 61 cput0 out true clock of low power differential cpu clock pair. 62 vddcpu pwr power s upply 3.3v nominal. 63 ck_pwrgd/pd# in notifies ck505 to sample latched inputs, or iamt entry/exit, or pwrdwn# mode 64 fslb/test_mode in 3.3v tolerant input for cpu frequency selection. refer to input electrical characteristics for vil_fs and vih_fs values. test_mode is a real time input to select between hi-z and ref/n divider mode while in test mode. refer to test clarification table.
11 ics9lprs365 datasheet 1218?09/01/10 ref cpu(1:0) cpu pll1 ss osc ref src(11-9,4:3, 7:6) pll2 non-ss pll3 ss 7 src8/cpu_itp pcif5 (4:0) src2/sata 27mhz/src1/se(2:1) se outputs s ata dot96mhz pci33mhz src src s r c _ m a i n pci33mhz differential output src0/dot96 48mhz 48mhz cpu fsla ckpwrgd/pd# pci_stop# cpu_stop# cr#_(a:h) 27_select tme, itp_en fslc/testsel fslb/testmode control logic x1 x2 27mhz_nonss ics9lprs365 follows intel ck505 yellow cover specification. this clock synthesizer provides a single chip solution for next generation p4 intel processors and intel chipsets. ics9lprs365 is driven with a 14.318mhz crystal. it also provides a tight ppm accuracy output for serial ata and pci-express support. general description block diagram power groups vdd gnd 49 52 cpuclk low power outputs 55 52 26, 36, 45 23, 29, 42 low power outputs 39 23, 29, 42 pll 1 20 19 low power outputs 16 19 pll 3 12 11 dot 96mhz low power outputs 911 61 58 28 usb 48 xtal, ref pciclk srcclk pin number description pll3/se master clock, analog
12 ics9lprs365 datasheet 1218?09/01/10 absolute maximum ratings parameter symbol conditions min max units notes maximum supply voltage vddxxx core/logic supply 4.6 v 1,2 maximum supply voltage vddxxx_io low voltage differential i/o supply 3.8 v 1,2 maximum input voltage v ih 3.3v lvcmos inputs 4.6 v 1,2,3 minimum input voltage v il any input gnd - 0.5 v 1,2 storage temperature ts - -65 150 c1,2 case temperature tcase - 115 c 1,2 input esd protection esd prot human body model 2000 v 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied, nor guaranteed. 3 maximum input voltage is not to exceed maximum vdd electrical characteristics - input/supply/common output parameters parameter symbol conditions min typical max units notes ambient operating temp tambient - 0 70 c 1 supply voltage vddxxx supply voltage 3.135 3.465 v 1 supply voltage vddxxx_io low-voltage differential i/o supply 1 3.465 v 1 input high voltage v ihse single-ended inputs 2 v dd + 0.3 v 1 input low voltage v ilse single-ended inputs v ss - 0.3 0.8 v 1 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input leakage current i inres inputs with pull or pull down resistors v in = v dd , v in = gnd -200 200 ua 1 output high voltage v ohs e single-ended outputs, i oh = -1ma 2.4 v 1 output low voltage v ols e single-ended outputs, i ol = 1 ma 0.4 v 1 output high voltage v ohdif differential outputs, i oh = tbd ma 0.7 0.9 v 1 output low voltage v oldif differential outputs, i ol = tbd ma 0.4 v 1 low threshold input- high voltage (test mode) v ih_fs_test 3.3 v +/-5% 2 v dd + 0.3 v 1 low threshold input- high voltage v ih_fs 3.3 v +/-5% 0.7 1.5 v 1 low threshold input- low voltage v il_fs 3.3 v +/-5% v ss - 0.3 0.35 v 1 i dd_default 3.3v supply, pll3 off 95 250 ma 1 i dd_pll3dif 3.3v supply, pll3 differential out 106 250 ma 1 i dd_pll3se 3.3v supply, pll3 single-ended out 101 250 ma 1 i dd_io 0.8v supply, differential io current, all outputs enabled 25 32 80 ma 1 i dd_pd3.3 3.3v supply, power down mode 26 30 ma 1 i dd_pdio 0.8v io supply, power down mode 0.23 0.5 ma 1 i dd_iamt3.3 3.3v supply, iamt mode 47 80 ma 1 i dd_iamt0.8 0.8v io supply, iamtmode 5 10 ma 1 input frequency f i v dd = 3.3 v 14.318 mhz 1 pin inductance l pin 7nh1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 c inx x1 & x2 pins 5 pf 1 spread spectrum modulation frequency f ssmod triangular modulation 30 33 khz 1 *t a = 0 - 70c; v dd = 3.3 v +/-5% operating supply current power down current iamt mode current input capacitance 1 guaranteed by design and characterization, not 100% tested in production.
13 ics9lprs365 datasheet 1218?09/01/10 electrical characteristics - smbus interface parameter symbol conditions min max units notes smbus voltage v dd 2.7 5.5 v 1 low-level output voltage v ol s mb @ i pullup 0.4 v 1 current sinking at v ol s m b = 0.4 v i pullup smb data pin 4 ma 1 sclk/sdata clock/data rise time t ri2c (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata clock/data fall time t fi2c (min vih + 0.15) to (max vil - 0.15) 300 ns 1 maximum smbus operating fre q uenc y f smbus block mode 100 khz 1 1 guaranteed by design and characterization, not 100% tested in production. ac electrical characteristics - input/common parameters parameter symbol conditions min max units notes clk stabilization t stab from vdd power-up or de- assertion of pd# to 1st clock 1.8 ms 1 tdrive_src t drsrc src output enable after pci_stop# de-assertion 15 ns 1,2 tdrive_pd# t drpd differential output enable after pd# de-assertion 300 us 1 tdrive_cpu t drsrc cpu output enable after cpu_stop# de-assertion 10 ns 1,2 tfall_pd# t fall 5ns1,2 trise_pd# t rise 5ns1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 optional. only applies when pci_stop# and/or cpu_stop# is present. fall/rise time of pd#, pci_stop# and cpu_stop# inputs ac electrical characteristics - low power differential outputs parameter symbol conditions min max units notes rising edge slew rate t slr differential measurement 2.5 8 v/ns 1,2 falling edge slew rate t flr differential measurement 2.5 8 v/ns 1,2 slew rate variation t slvar single-ended measurement 20 % 1 maximum output voltage v high includes overshoot 1150 mv 1 minimum output voltage v low includes undershoot -300 mv 1 differential voltage swing v swing differential measurement 300 mv 1 crossing point voltage v xabs single-ended measurement 300 550 mv 1,3,4 crossing point variation v xabsvar single-ended measurement 140 mv 1,3,5 duty cycle d cyc differential measurement 45 55 % 1 cpu jitter - cycle to cycle cpuj c2c differential measurement 85 ps 1 src jitter - cycle to cycle srcj c2c differential measurement 125 ps 1 dot jitter - cycle to cycle dotj c2c differential measurement 250 ps 1 cpu[1:0] skew cpu skew10 differential measurement 100 ps 1 cpu[2_itp:0] skew cpu skew20 differential measurement 150 ps 1 src[10:0] skew src skew differential measurement tbd ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5%; c l =5pf, r s =22 ? (unless specified otherwise.) 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing centered around differential zero 3 vxabs is defined as the voltage where clk = clk# 4 only applies to the differential rising edge (clk rising and clk# falling) 5 defined as the total variation of all crossing voltages of clk rising and clk# falling. matching applies to rising edge rate of clk and falling edge of clk#.
14 ics9lprs365 datasheet 1218?09/01/10 intentional pci clock to clock delay 200 ps nominal steps pci0 pci1 pci2 pci3 pci4 pci_f5 1.0ns electrical characteristics - pciclk/pciclk_f parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 33.33mhz output nominal 30.00900 ns 2 33.33mhz output spread 30.15980 ns 2 absolute min/max period t abs 33.33mhz output nominal/spread 29.49100 30.65980 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -33 ma 1 v oh @max = 3.135 v -33 ma 1 v ol @ min = 1.95 v 30 ma 1 v ol @ max = 0.4 v 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 skew t skew v t = 1.5 v 250 ps 1 intentional pci-pci delay t delay v t = 1.5 v ps 1,3 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 500 ps 1 *t a = 0 - 70c; v dd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz output high current i oh output low current i ol 29.99100 t period 3 see pci clock-to-clock delay figure 200 nominal clock period
15 ics9lprs365 datasheet 1218?09/01/10 electrical characteristics - usb48mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -100 100 ppm 1,2 clock period t period 48.00mhz output nominal 20.83125 20.83542 ns 2 absolute min/max period t abs 48.00mhz output nominal 20.48130 21.18540 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 2 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 2 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 350 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz output high current i oh i ol output low current electrical characteristics - se 24.576mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t period 24.576mhz output nominal 40.70231 40.67790 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 v oh @min = 1.0 v -29 ma 1 v oh @max = 3.135 v -23 ma 1 v ol @ min = 1.95 v 29 ma 1 v ol @ max = 0.4 v 27 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter, cycle to cycle t jcyc-cyc v t = 1.5 v 500 ps 1 *ta = 0 - 70c; supply voltage vdd = 3.3 v +/-5% 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz output low current i ol output high current i oh
16 ics9lprs365 datasheet 1218?09/01/10 electrical characteristics - ref-14.318mhz parameter symbol conditions min max units notes long accuracy ppm see tperiod min-max values -300 300 ppm 1,2 clock period t period 14.318mhz output nominal 69.8203 69.8622 ns 2 absolute min/max period t abs 14.318mhz output nominal 69.8203 70.86224 ns 2 output high voltage v oh i oh = -1 ma 2.4 v 1 output low voltage v ol i ol = 1 ma 0.4 v 1 output high current i oh v oh @min = 1.0 v, v oh @max = 3.135 v -33 -33 ma 1 output low current i ol v ol @min = 1.95 v, v ol @max = 0.4 v 30 38 ma 1 rising edge slew rate t slr measured from 0.8 to 2.0 v 1 4 v/ns 1 falling edge slew rate t flr measured from 2.0 to 0.8 v 1 4 v/ns 1 duty cycle d t1 v t = 1.5 v 45 55 % 1 jitter t jcyc-cyc v t = 1.5 v 1000 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 all long term accuracy and clock period specifications are guaranteed assuming that refout is at 14.31818mhz preferred drive strengths using ck505 clock sources. transmission lines to load do not share series resistors. desktop (zo=50 ? ) and mobile (zo=55 ? ) have the same drive strength. 1 load rs = 2 loads rs= 3 loads rs = 1 0.56 / 33 (17 ? ) 33 ? [39 ? ] - - 2 0.92 / 66 (14 ? ) 39 ? [43 ? ]22 ? [27 ? ]- 3 1.15 / 99 (11.6 ? ) 43 ? [43 ? ] 27 ? [33 ? ]15 ? [22 ? ] d.c.drive strength number of loads to drive number of loads actually driven. [zo=55 ? ] match point for n & p voltage / current (ma)
17 ics9lprs365 datasheet 1218?09/01/10 fs l c 2 b0b7 fs l b 1 b0b6 fs l a 1 b0b5 cpu mhz src mhz pci mhz ref mhz u sb mhz dot mhz 000266.66 001133.33 010200.00 011166.66 100333.33 101100.00 110400.00 111 1. fs l a and fs l b are low-threshold inputs.please see v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. also refer to the test clarification table. 2. fs l c is a three-level input. please see the v il_fs and v ih_fs specifications in the input/supply/common output parameters table for correct values. table 1: cpu fre q uenc y select table 96.00 100.00 33.33 14.318 48.00 reserved pin17 (tssop) / pin24 ( mlf ) pin18 (tssop) / pin25 ( mlf ) spread mhz mhz % 0 000 0 0 0 0 0 1 100.00 100.00 0.5% down spread srcclk1 from src_main 0 0 0 1 0 100.00 100.00 0.5% down spread only srcclk1 from pll3 0 0 0 1 1 100.00 100.00 1% down spread only srcclk1 from pll3 0 0 1 0 0 100.00 100.00 1.5% down spread only srcclk1 from pll3 0 0 1 0 1 100.00 100.00 2% down spread only srcclk1 from pll3 0 0 1 1 0 100.00 100.00 2.5% down spread only srcclk1 from pll3 0 011 1 n/a n/a n/a n/a 0 1 0 0 0 24.576 24.576 none 24.576mhz on se1 and se2 0 1 0 0 1 24.576 98.304 none 24.576mhz on se1, 98.304mhz on se2 0 1 0 1 0 98.304 98.304 none 98.304mhz on se1 and se2 0 1 0 1 1 27.000 27.000 none 27mhz on se1 and se2 0 1 1 0 0 25.000 25.000 none 25mhz on se1 and se2 0 110 1 n/a n/a n/a n/a 0 111 0 n/a n/a n/a n/a 0 111 1 n/a n/a n/a n/a 1 000 0 n/a n/a n/a 1 000 1 n/a n/a n/a 1 001 0 27mhz_nonss 27mhz_ss 0.5% down spread 1 001 1 27mhz_nonss 27mhz_ss 1% down spread 1 010 0 27mhz_nonss 27mhz_ss 1.5% down spread 1 010 1 27mhz_nonss 27mhz_ss 2% down spread 1 011 0 27mhz_nonss 27mhz_ss 0.75% down spread 1 011 1 27mhz_nonss 27mhz_ss 1.25% down spread 1 100 0 27mhz_nonss 27mhz_ss 1.75% down spread 1 100 1 27mhz_nonss 27mhz_ss 0.5% center spread 1 101 0 27mhz_nonss 27mhz_ss 0.75% center spread 1 101 1 n/a n/a 1 110 0 n/a n/a 1 110 1 n/a n/a 1 111 0 n/a n/a 1 111 1 n/a n/a comment pll 3 disabled b1b1 b1b4 b1b3 b1b2 27_select table 2: pll3 quick confi g uration
18 ics9lprs365 datasheet 1218?09/01/10 1 11 x enable running running running running 0 x x x enable low/20k low low/20k low 1 0 x x enable high low high low 1x x x disable low/20k low low/20k low running running low/20k low src/lcd src#/lcd# src/lcd src#/lcd# 1x 10 enable running running running running running running 0 x x x enable low/20k low low/20k low low/20k low 1x 0 x enable running running high low running running 1x x 1 enable running running low/20k low running running 1x x x disable low/20k low low/20k low low/20k low low/20k low low/20k low low/20k low pcif/pci pcif/pci free-run stoppable 1x 1 x enable running running running running 0 x x x enable low low low low 1x 0 x enable running low running running 1x x x disable low low low low low low low low usb ref m1 m1 pd# cpu_stop# pci_stop# cr# smbus register oe singled-ended power management table dot dot# free-run pci stoppable/cr selected cpu(0,2) cpu(0,2)# m1 pd# cpu_stop# pci_stop# cr# smbus register oe src, lcd, dot power management table cpu power management table pd# cpu_stop# pci_stop# cr# smbus register oe cpu1 cpu1# table 3: io_vout select table b9b2 b9b1 b9b0 io_vout 000 0.3v 001 0.4v 010 0.5v 011 0.6v 100 0.7v 101 0.8v 110 0.9v 111 1.0v
19 ics9lprs365 datasheet 1218?09/01/10 general smbus serial interface information for the ics9lprs365 how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the beginning byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) starts sending byte n through byte n + x -1 ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) will send a separate start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
20 ics9lprs365 datasheet 1218?09/01/10 byte 0 fs readback and pll selection register bit pin name description type 0 1 default 7 - fslc cpu freq. sel. bit (most significant) r latch 6 - fslb cpu freq. sel. bit r latch 5 - fsla cpu freq. sel. bit (least si g nificant) r latch 4- iamt_en set via smbus or dynamically by ck505 if detects dynamic m1 rw (sticky bit) legacy mode iamt enabled 0 3 reserved reserved rw 0 2 - src_main_sel select source for src main rw src main = pll1 src main = pll3 0 1 - sata_sel select source for sata clock rw sata = src_main sata = pll2 0 0- pd_restore if config saved, on deassert return to last known state else clear all config as if cold power on and go to latches open state rw configuration not saved configuration saved 1 byte 1 dot96 select and pll3 quick config register bit pin name description type 0 1 default 7 13/14 src0_sel select src0 or dot96 r src0 dot96 note 1 6 - pll1_ssc_sel select 0.5% down or center ssc rw down spread center spread 0 5reserved rw 0 4 17/18 pll3_cf3 pll3 quick confi g bit 3 rw 0 3 pll3_cf2 pll3 quick config bit 2 rw 0 2 pll3_cf1 pll3 quick config bit 1 rw 1 1 pll3_cf0 pll3 quick confi g bit 0 rw 0 0 pci_sel pci_sel rw pci from pll1 pci from pll3 1 note 1 : when 27_select pin = 0, b1b7 pwd = 1, , when 27_select pin = 1, pwd = 0 byte 2 output enable register bit pin name description type 0 1 default 7ref_oe output enable for ref, if disabled output is tri- stated rw output disabled output enabled 1 6 usb_oe output enable for usb rw output disabled output enabled 1 5 pcif5_oe output enable for pci5 rw output disabled output enabled 1 4 pci4_oe output enable for pci4 rw output disabled output enabled 1 3 pci3_oe output enable for pci3 rw output disabled output enabled 1 2 pci2_oe output enable for pci2 rw output disabled output enabled 1 1 pci1_oe output enable for pci1 rw output disabled output enabled 1 0 pci0_oe output enable for pci0 rw output disabled output enabled 1 byte 3 output enable register bit pin name description type 0 1 default 7 src11_oe output enable for src11 rw output disabled output enabled 1 6 src10_oe output enable for src10 rw output disabled output enabled 1 5 src9_oe output enable for src9 rw output disabled output enabled 1 4 src8/itp_oe output enable for src8 or itp rw output disabled output enabled 1 3 src7_oe output enable for src7 rw output disabled output enabled 1 2 src6_oe output enable for src6 rw output disabled output enabled 1 1 reserved reserved rw output disabled output enabled 1 0 src4_oe output enable for src4 rw output disabled output enabled 1 see table 2: pin17, 18 configuration only applies if byte 0, bit 2 = 0. see table 1 : cpu frequency select table
21 ics9lprs365 datasheet 1218?09/01/10 byte 4 output enable and spread spectrum disable register bit pin name description type 0 1 default 7 src3_oe out p ut enable for src3 rw out p ut disabled out p ut enabled 1 6 sata/src2_oe out p ut enable for sata/src2 rw out p ut disabled out p ut enabled 1 5 src1_oe out p ut enable for src1 rw out p ut disabled out p ut enabled 1 4 src0/dot96_oe output enable for src0/dot96 rw output disabled output enabled 1 3 cpu1_oe out p ut enable for cpu1 rw out p ut disabled out p ut enabled 1 2 cpu0_oe out p ut enable for cpu0 rw out p ut disabled out p ut enabled 1 1 pll1_ssc_on enable pll1's s p read modulation rw s p read disabled s p read enabled 1 0 pll3_ssc_on enable pll3's spread modulation rw spread disabled spread enabled 1 byte 5 clock request enable/configuration register bit pin name description type 0 1 default 7 cr#_a_en enable cr#_a (clk req), pci0_oe must be = 0 for this bit to take effect rw disable cr#_a enable cr#_a 0 6 cr#_a_sel sets cr#_a to control either src0 or src2 rw cr#_a -> src0 cr#_a -> src2 0 5 cr#_b_en enable cr#_b (clk req) rw disable cr#_b enable cr#_b 0 4 cr#_b_sel sets cr#_b -> src1 or src4 rw cr#_b -> src1 cr#_b -> src4 0 3 cr#_c_en enable cr#_c ( clk re q) rw disable cr#_c enable cr#_c 0 2 cr#_c_sel sets cr#_c -> src0 or src2 rw cr#_c -> src0 cr#_c -> src2 0 1 cr#_d_en enable cr#_d (clk req) rw disable cr#_d enable cr#_d 0 0 cr#_d_sel sets cr#_d -> src1 or src4 rw cr#_d -> src1 cr#_d -> src4 0 byte 6 clock request enable/configuration and stop control register bit pin name description type 0 1 default 7 cr#_e_en enable cr#_e ( clk re q) -> src6 rw disable cr#_e enable cr#_e 0 6 cr#_f_en enable cr#_f ( clk re q) -> src8 rw disable cr#_f enable cr#_f 0 5 cr#_g_en enable cr#_g ( clk re q) -> src9 rw disable cr#_g enable cr#_g 0 4 cr#_h_en enable cr#_h (clk req) -> src10 rw disable cr#_h enable cr#_h 0 3 reserved reserved rw 0 2 reserved reserved rw 0 1 sscd_stp_crtl if set, lcd_ss stops with pci_stop# rw free running stops with pci_stop# assertion 0 0 src_stp_crtl if set, srcs stop with pci_stop# rw free running stops with pci_stop# assertion 0 byte 7 vendor id/ revision id bit pin name description type 0 1 default 7 rev code bit 3 r 0 6 rev code bit 2 r 0 5 rev code bit 1 r 1 4 rev code bit 0 r 0 3 vendor id bit 3 r 0 2 vendor id bit 2 r 0 1 vendor id bit 1 r 0 0 vendor id bit 0 r 1 revision id vendor id ics is 0001, binary vendor specific
22 ics9lprs365 datasheet 1218?09/01/10 byte 8 device id and output enable register bit pin name description type 0 1 default 7 device_id3 r 1 6 device_id2 r 1 5 device_id1 r 0 4 device_id0 r 1 3 reserved reserved rw - - 0 2 reserved reserved rw - - 0 1 se1_oe output enable for se1 rw disabled enabled 27_select power on latch 0 se2_oe output enable for se2 rw disabled enabled 27_select power on latch byte 9 output control register bit pin name description type 0 1 default 7 pcif5 stop en allows control of pcif5 with assertion of pci_stop# rw free running stops with pci_stop# assertion 0 6 tme_readback truested mode enable (tme) strap status r normal operation no overclocking 0 5 ref strength sets the ref out p ut drive stren g th rw 1x ( 2loads ) 2x ( 3 loads ) 1 4 test mode select allows test select, i g nores ref/fsc/testsel rw out p uts hi-z out p uts = ref/n 0 3 test mode entry allows entry into test mode, ignores fsb/testmode rw normal operation test mode 0 2 io_vout2 io output voltage select (most significant bit) rw 1 1 io_vout1 io out p ut volta g e select rw 0 0 io_vout0 io output voltage select (least significant bit) rw 1 byte 10 free-running control register bit pin name description type 0 1 default 7 27_selec latch read back readback of 27_select latch r dot96/ lcd_ss / se src0/ 27mhz 27_select latch 6reserved reserved rw -- 1 5reserved reserved rw -- 1 4 cpu1_amt_en m1 mode clk enable rw disable enable 1 3 reserved reserved rw -- 1 2 cpu 2 stop enable enables control of cpu2 with cpu_stop# rw free runnin g sto pp able 1 1 cpu 1 stop enable enables control of cpu1 with cpu_stop# rw free running stoppable 1 0 cpu 0 stop enable enables control of cpu 0 with cpu_stop# rw free running stoppable 1 byte 11 strength control register bit pin name description type 0 1 default 7 48mhz rw 1x 2x 0 6 pcif5 rw 1x 2x 0 5pci4 rw1x2x0 4pci3 rw1x2x0 3pci2 rw1x2x0 2pci1 rw1x2x0 1pci0 rw1x2x0 0 reserved reserved rw -- 0 see table 3: v_io selection (default is 0.8v) table of device identifier codes, used for differentiating between ck505 package options, etc. see device id table reserved
23 ics9lprs365 datasheet 1218?09/01/10 byte 12 byte count register bit pin name description type 0 1 default 7reserved rw 0 6reserved rw 0 5 bc5 rw 0 4 bc4 rw 0 3 bc3 rw 1 2 bc2 rw 1 1 bc1 rw 0 0 bc0 rw 1 byte 13 vco frequency control register pll1 bit pin name description type 0 1 default 7 n div8 n divider 8 rw - - x 6 n div9 n divider 9 rw - - x 5 m div5 rw - - x 4 m div4 rw - - x 3 m div3 rw - - x 2 m div2 rw - - x 1 m div1 rw - - x 0 m div0 rw - - x byte 14 vco frequency control register pll1 bit pin name description type 0 1 default 7 n div7 rw - - x 6 n div6 rw - - x 5 n div5 rw - - x 4 n div4 rw - - x 3 n div3 rw - - x 2 n div2 rw - - x 1 n div1 rw - - x 0 n div0 rw - - x byte 15 spread spectrum control register pll1 bit pin name description type 0 1 default 7 ssp7 rw - - x 6 ssp6 rw - - x 5 ssp5 rw - - x 4 ssp4 rw - - x 3 ssp3 rw - - x 2 ssp2 rw - - x 1 ssp1 rw - - x 0 ssp0 rw - - x byte 16 spread spectrum control register pll1 bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 ssp14 rw - - x 5 ssp13 rw - - x 4 ssp12 rw - - x 3 ssp11 rw - - x 2 ssp10 rw - - x 1 ssp9 rw - - x 0 ssp8 rw - - x these spread spectrum bits will program the spread pecentage. contact ics for the correct values. the decimal representation of n div (9:0) is equal to vco divider value. default at power up = latch-in or byte 0 rom table. the decimal representation of m div (5:0) is equal to reference divider value. default at power up = latch-in or byte 0 rom table. these spread spectrum bits will program the spread pecentage. contact ics for the correct values. read back byte count register, max bytes = 32
24 ics9lprs365 datasheet 1218?09/01/10 byte 17 vco frequency control register pll3 bit pin name description type 0 1 default 7 n div8 n divider 8 rw - - x 6 n div9 n divider 9 rw - - x 5 m div5 rw - - x 4 m div4 rw - - x 3 m div3 rw - - x 2 m div2 rw - - x 1 m div1 rw - - x 0 m div0 rw - - x byte 18 vco frequency control register pll3 bit pin name description type 0 1 default 7 n div7 rw - - x 6 n div6 rw - - x 5 n div5 rw - - x 4 n div4 rw - - x 3 n div3 rw - - x 2 n div2 rw - - x 1 n div1 rw - - x 0 n div0 rw - - x byte 19 spread spectrum control register pll3 bit pin name description type 0 1 default 7 ssp7 rw - - x 6 ssp6 rw - - x 5 ssp5 rw - - x 4 ssp4 rw - - x 3 ssp3 rw - - x 2 ssp2 rw - - x 1 ssp1 rw - - x 0 ssp0 rw - - x byte 20 spread spectrum control register pll3 bit pin name description type 0 1 default 7 reserved reserved rw - - 0 6 ssp14 rw - - x 5 ssp13 rw - - x 4 ssp12 rw - - x 3 ssp11 rw - - x 2 ssp10 rw - - x 1 ssp9 rw - - x 0 ssp8 rw - - x byte 21 m/n enables bit pin name description rw 0 1 default 7 reserved rw 0 6 reserved rw 0 5 reserved rw 0 4 reserved rw 0 3 reserved rw 0 2 reserved rw 0 1 m/n enable cpu pll m/n enable rw disable enable 0 0 m/n enable src/pci pll m/n enable rw disable enable 0 the decimal representation of m div (5:0) is equal to reference divider value. default at power up = latch-in or byte 0 rom table. *these bits are disabled if tme is latched to 1 the decimal representation of n div (9:0) is equal to vco divider value. default at power up = latch-in or byte 0 rom table. these spread spectrum bits will program the spread pecentage. contact ics for the correct values. these spread spectrum bits will program the spread pecentage. contact ics for the correct values.
25 ics9lprs365 datasheet 1218?09/01/10 test clarification table comments fslc/ test_sel hw pin fslb/ test_mode hw pin test entry bit b9b3 ref/n or hi-z b9b4 output <2.0v x 0 0 normal >2.0v 0 x 0 hi-z >2.0v 0 x 1 ref/n >2.0v 1 x 0 ref/n >2.0v 1 x 1 ref/n <2.0v x 1 0 hi-z <2.0v x 1 1 ref/n hw sw power-up w/ test_sel = 1 to enter test mode cycle power to disable test mode fslc./test_sel -->3-level latched input if power-up w/ v>2.0v then use test_sel if power-up w/ v<2.0v then use fslc fslb/test_mode -->low vth input test_mode is a real time input if test_sel hw pin is 0 during power-up, test mode can be invoked through b9b3. if test mode is invoked by b9b3, only b9b4 is used to select hi-z or ref/n fslb/test_mode pin is not used. cycle power to disable test mode, one shot control b9b3: 1= enter test mode, default = 0 (normal operation) b9b4: 1= ref/n, default = 0 (hi-z)
26 ics9lprs365 datasheet 1218?09/01/10 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a--1.20--.047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 64 16.90 17.10 .665 .673 10-0039 6.10 mm. bod y , 0.50 mm. pitch tssop ( 240 mil ) ( 20 mil ) symbol in millimeters in inches common dimensions common dimensions see variations see variations 8.10 basic 0.319 basic 0.50 basic 0.020 basic see variations see variations n d mm. d (inch) reference doc.: jedec publication 95, mo-153 marking diagram
27 ics9lprs365 datasheet 1218?09/01/10 dimensions option 1 dimensions (mm) option 2 dimensions (mm) symbol min. max. symbol min. max. a0.81.0 a0.81.0 n 64 a1 0 0.05 a1 0 0.05 n d 16 a3 a3 n e 16 b 0.18 0.3 b 0.18 0.3 ee d x e basic d x e basic d2 min. / max. 7.00 7.25 d2 min. / max. 6.00 6.25 e2 min. / max. 7.00 7.25 e2 min. / max. 6.00 6.25 l min. / max. 0.30 0.50 l min. / max. 0.30 0.50 thermally enhanced, ve ry thin, fine pitch quad flat / no lead plastic package 0.25 reference 0.50 basic 9.00 x 9.00 0.25 reference 0.50 basic 9.00 x 9.00 ordering information part/order number marking shipping packaging package temperature 9lprs365bglf tubes 9lprs365bglft tape and reel 9LPRS365BKLF tubes 9LPRS365BKLFt tape and reel see page 26 64-tssop 0 to +70 c see page 27 64-vqfn marking diagram
28 ics9lprs365 datasheet 1218?09/01/10 revision history rev. issue date description page # 0.1 4/5/2006 initial release - 0.2 7/11/2006 updated electrical characteristics. 12 0.3 8/25/2006 1. updated pin description and i2c. 2-5, 7-10, 22-23 0.4 10/25/2006 added byte 21. 23 0.5 11/22/2006 1. updated pin description of pin #33 (tssop) and pin #40 (qfn) 2. updated b1b0 in i2c. 4,9, 19 0.6 11/29/2006 updated ds to reflect revision c changes various 0.65 3/7/2007 updated feautres/benefits. 1 0.7 3/9/2007 updated supply currents in electrical characteristics. 12 0.8 3/20/2007 updated b y te 5 bit 7 description in the i2c 20 0.9 4/3/2007 updated b[11,21] in the i2c 23 0.91 5/21/2007 removed pull-up/pull-down footnotes. 1 0.92 7/16/2007 updated case temperature in electrical characteristics. 12 0.93 4/8/2008 1. updated mlf ordering information. 2. reformatted dimensions tables. 26 0.94 6/3/2008 updated pin description and smbus. various 0.95 9/18/2008 updated electrical characteristics. various 0.96 12/12/2008 added ds-loadin g table. 16 0.97 1/28/2009 update table2, smbus byte1 table, added 27_select tables for tssop and mlf various 0.98 4/1/2009 update sel27 and itp_en pin descriptions. various 0.99 9/9/2009 added updated orderin g information table and markin g dia g rams. 26, 27 a 9/1/2010 updated pll3 quick configuration table 17

▲Up To Search▲

Price & Availability of 9LPRS365BKLF

	To Download 9LPRS365BKLF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .